DesignCon 2005 Design of a Low-Power Differential Repeater Using Low Voltage and Charge Recycling

Advances in System-on-Chip (SoC) design have emphasized the need for driving long on-chip differential traces. The delay of long traces has traditionally been handled by inserting repeaters at periodic intervals. The repeater method reduces the delay at the expense of increased power consumption. At the same time, power is a major design consideration in SoC design, motivating a driver methodology that has comparable delay to the repeater approach, with lower power consumption. This paper presents the design of a differential driver using low-voltage swing and charge recycling. The low-voltage design is shown to reduce the overall power by 37% and the Power-Delay-Product by 32% compared to traditional full-swing differential repeaters. By including charge recycling, the power can be reduced by 43%, which includes the power consumed by the associated control circuitry. This indicates that the charge recycling low voltage differential driver methodology is valuable when power is a major design concern. Author(s) Biography Brock J. LaMeres received his BSEE from Montana State University in 1998 and his MSEE from the University of Colorado in 2001. He is currently a Ph.D. candidate at the University of Colorado where his research focus is VLSI Circuit Design and High-Speed I/O for next generation IC’s. For the past 6 years he has worked as a hardware design engineer for Agilent Technologies in Colorado Springs where he designs logic analyzer probes and acquisition boards. LaMeres has published 25 technical articles in the area of signal integrity and has a patent in the field of logic analyzer probing. LaMeres is a registered Professional Engineer in the State of Colorado. Sunil P. Khatri is an Assistant Professor in the Department of Electrical Engineering at Texas A&M University. He is affiliated with the VLSI CAD group. He completed his Ph.D. from the University of California, Berkeley in 1999. Before this, he worked with Motorola, Inc on the designs of the MC88110 and PowerPC 603 RISC Microprocessors. Khatri obtained his M.S from the University of Texas at Austin, which followed his B.Tech. from the Indian Institute of Technology, Kanpur. His research is in the areas of VLSI Design and VLSI CAD. Some recent areas of interest are design automation for datapath circuits, cross-talk avoidance in on-chip buses, leakage-power reduction, extreme low power circuit design, asynchronous circuit design methodologies, timing estimation, efficient test generation, fast logic simulation and cross-talk immune VLSI design.